exp08-priority-encoder

The question, verbatim

Design and simulate a 4-to-2 priority encoder using Logisim. Your circuit should include an enable input and a 'valid output' signal. Explain your design choices, show the truth table, and test all possible input combinations. Discuss how your circuit behaves when multiple inputs are active and when the enable signal is disabled.

extractor: human transcription from screenshot, verified against the image character by character
file: lab manual, section 8.2 Open Ended Question (screenshot)

What it asks for:

show the truth table answered by truth_table
test all possible input combinations answered by truth_table
Explain your design choices prose
Discuss how your circuit behaves when multiple inputs are active and when the enable signal is disabled prose

Results

measurement	value	run	how	standing
truth_table	no single value — see the table below	exhaustive	simulation / logisim-evolution	EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement

truth_table

EN	I3	I2	I1	I0	Y1	Y0	V
0	0	0	0	0	0	0	0
0	0	0	0	1	0	0	0
0	0	0	1	0	0	0	0
0	0	0	1	1	0	0	0
0	0	1	0	0	0	0	0
0	0	1	0	1	0	0	0
0	0	1	1	0	0	0	0
0	0	1	1	1	0	0	0
0	1	0	0	0	0	0	0
0	1	0	0	1	0	0	0
0	1	0	1	0	0	0	0
0	1	0	1	1	0	0	0
0	1	1	0	0	0	0	0
0	1	1	0	1	0	0	0
0	1	1	1	0	0	0	0
0	1	1	1	1	0	0	0
1	0	0	0	0	0	0	0
1	0	0	0	1	0	0	1
1	0	0	1	0	0	1	1
1	0	0	1	1	0	1	1
1	0	1	0	0	1	0	1
1	0	1	0	1	1	0	1
1	0	1	1	0	1	0	1
1	0	1	1	1	1	0	1
1	1	0	0	0	1	1	1
1	1	0	0	1	1	1	1
1	1	0	1	0	1	1	1
1	1	0	1	1	1	1	1
1	1	1	0	0	1	1	1
1	1	1	0	1	1	1	1
1	1	1	1	0	1	1	1
1	1	1	1	1	1	1	1

read in compatibility mode: the file was written by original Logisim (2.7.1), not Logisim Evolution

Regime checks

assertion	run	verdict	what it examined
no_floating_inputs	exhaustive	held	20 input port(s) across 16 components, each for membership of a net that has a driver
all_outputs_driven	exhaustive	held	3 output pin(s), each for a net carrying a driving port
no_combinational_loops	exhaustive	held	the driver graph over 16 components, depth-first, for any cycle

Checks that did not run

SKIPPED geometric round trip — the .circ geometric parser is not built (deferred to v1.1 with check-mine mode), so no round trip ran. Structure, types, pins and labels were checked here; geometry was not. Note what replaces it and is stronger: Logisim itself evaluates the emitted file, so a geometry bug shows up as a wrong truth table rather than as our parser agreeing with our emitter's mistake.
SKIPPED device policy — the logisim-2.7.1 target has no device models, so no part was chosen, substituted, or synthesised

Download

exp08-priority-encoder.circ (logisim-circuit)
verified byte-identical to exhaustive.circ, the file logisim-evolution actually evaluated — compared, not assumed
sha256 0994fd86e40987e35cc0e27fdf703abdfc9692a32d844e37577e99b43ea310a2

The layout in these files is generated mechanically — a grid for LTspice, columns by logic depth for Logisim. It is correct, not pretty, and it will not resemble a hand-drawn schematic.

Devices and design choices

Design notes

All 4 design notes are quoted in full under Explanations below, where quoting them is the answer to an ask. They are not repeated here.

Explanations

These answers are prose. Nothing can verify them the way a simulator verifies a number, so each one shows what it rests on: quoted design rationales, or the computed rows it describes.

Explain your design choices

tier: prose_from_design

constraint: primitives_only: gate primitives only; Logisim's built-in Plexers Priority Encoder is banned
the question does NOT ask for primitives only. It is our constraint, added because dropping in the library component satisfies the wording and defeats the exercise entirely. Declared here rather than smuggled in, because presenting our pedagogical choice as the question's requirement would misrepresent the assignment. [generated, reviewed at input gate]

priority order: I3 highest, I0 lowest
conventional MSB-first priority; the question does not state an order, so this is a choice and the truth table only makes sense once it is stated [generated, reviewed at input gate]

enable gating: AND the enable into all three outputs
EN=0 then forces Y1=Y0=V=0, so a disabled encoder is unambiguous rather than showing a stale code. The question requires an enable input but does not define disabled-output behaviour. [generated, reviewed at input gate]

signal naming: inputs I3..I0, outputs Y1 (MSB), Y0 (LSB), V (valid), enable EN
the question names none of them. Recorded because the human implementation cross-check (tests/fixtures/logisim/exp8_gates.circ) uses D3..D0 / OUT 1 / OUT 2 / V, and comparing the two requires a stated name mapping rather than an assumed one. [generated, reviewed at input gate]

This tier generates no text. The choices above, and the reasons for them, are the answer — which is why it is the only prose here that nothing had to write.

Discuss how your circuit behaves when multiple inputs are active and when the enable signal is disabled

tier: prose_from_results

two or more data inputs active, enable on

11 of 32 rows of truth_table, computed by logisim-evolution. EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement

EN	I3	I2	I1	I0	Y1	Y0	V
1	0	0	1	1	0	1	1
1	0	1	0	1	1	0	1
1	0	1	1	0	1	0	1
1	0	1	1	1	1	0	1
1	1	0	0	1	1	1	1
1	1	0	1	0	1	1	1
1	1	0	1	1	1	1	1
1	1	1	0	0	1	1	1
1	1	1	0	1	1	1	1
1	1	1	1	0	1	1	1
1	1	1	1	1	1	1	1

enable disabled

16 of 32 rows of truth_table, computed by logisim-evolution. EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement

I3	I2	I1	I0
0	0	0	0
0	0	0	1
0	0	1	0
0	0	1	1
0	1	0	0
0	1	0	1
0	1	1	0
0	1	1	1
1	0	0	0
1	0	0	1
1	0	1	0
1	0	1	1
1	1	0	0
1	1	0	1
1	1	1	0
1	1	1	1

With the enable high, every row above resolves to the index of the highest-numbered active input and to nothing else. The seven rows with I3 high all read Y1 Y0 = 1 1, the three where I2 is the highest active input read 1 0, and the single row where I1 is highest reads 0 1 — in each case the lower-numbered inputs that are also high change nothing. That is the whole difference between a priority encoder and a plain encoder: a plain one would assert several outputs at once here and produce a code that means nothing. With the enable low, all sixteen rows read Y1 = Y0 = V = 0 whatever the data inputs do, so a disabled encoder never presents a stale code. Note the limit the table also shows: EN = 0 with every input high is indistinguishable at the output pins from EN = 1 with no input active — both are 0 0 0. V separates 'a valid code is on the outputs' from 'there is nothing to report'; it does not separate disabled from idle, and no output here does.

[generated, reviewed at input gate]

A human confirmed this text against exactly these rows. Check it against them yourself — that is what it is for.