exp03-regulated-supply

The question, verbatim

Design and simulate a regulated 6.2 V DC power supply using LTspice. The circuit should consist of a bridge rectifier, a C-L-C smoothing filter with C = 470 µF and L = 1 mH, followed by a Zener-diode voltage regulator. The bridge rectifier is driven by a 12 V RMS, 50 Hz AC supply, and a 1 kΩ resistive load is connected at the regulated output. Obtain and observe the input AC waveform, bridge rectifier output waveform, C-L-C filter output waveform, regulated DC output waveform, and load current waveform using LTspice.

extractor: human transcription from screenshot
file: lab manual, Experiment 3 open ended question (screenshot)

What it asks for:

input AC waveform answered by v_in_wave
bridge rectifier output waveform answered by v_rect_wave
C-L-C filter output waveform answered by v_filt_wave
regulated DC output waveform answered by v_out_wave
load current waveform answered by i_load_wave

Results

measurement	value	run	how	standing
v_in_wave	8.139164439895255e-06 = stats.mean	waveforms	simulation / ltspice	EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement max = 16.97048056125641, mean = 8.139164439895255e-06, min = -16.970591485500336, ripple_pp = 33.941072046756744, rms = 12.00014114961263
v_rect_wave	15.228354975039663 = stats.mean	waveforms	simulation / ltspice	EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement max = 15.732717514038086, mean = 15.228354975039663, min = 14.69326114654541, ripple_pp = 1.0394563674926758, rms = 15.229587921210383
v_filt_wave	15.228859098364538 = stats.mean	waveforms	simulation / ltspice	EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement max = 15.802033424377441, mean = 15.228859098364538, min = 14.629167556762695, ripple_pp = 1.172865867614746, rms = 15.23079050778252
v_out_wave	6.249992867799464 = stats.mean	waveforms	simulation / ltspice	EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement max = 6.251878261566162, mean = 6.249992867799464, min = 6.247890472412109, ripple_pp = 0.003987789154052734, rms = 6.249992921904045
i_load_wave	0.0062499928708683 = stats.mean	waveforms	simulation / ltspice	EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement max = 0.006251878570765257, mean = 0.0062499928708683, min = 0.006247890647500753, ripple_pp = 3.987923264503479e-06, rms = 0.006249992924972993

assertion	run	verdict	what it examined
zener_in_breakdown	waveforms / DZ	held	I(DZ) against a 0.0001 A minimum reverse current, and its terminal voltage against Vz=6.2 V, at 1115 sweep points of run 'waveforms'

Download

exp03-regulated-supply.asc (ltspice-schematic)
verified emitted from the same circuit description that was simulated, and round-trips through the geometric parser. The exact bytes were not the ones handed to LTspice: the deliverable carries every run, with one active and the rest commented
sha256 ffb91c6b0b6afa93467a95827153f53734379ae9ca1f6e2bfd0f52757734c10b
exp03-regulated-supply.plt (ltspice-plot)
UNVERIFIED batch mode does not read .plt, so no machine check exists for plot files; transcribed from LTspice's own examples, pending one visual confirmation in the GUI
sha256 678d4e19bc5d789ecb5e1634bdfe71f066c187887f57e84f4aa92c282554f8b2

The layout in these files is generated mechanically — a grid for LTspice, columns by logic depth for Logisim. It is correct, not pretty, and it will not resemble a hand-drawn schematic.

Devices and design choices

ref	part	policy	model card	why
D1	1N4007	nearest		question names no diode; using 1N4007 (general-purpose rectifier default)
D2	1N4007	nearest		question names no diode; using 1N4007 (general-purpose rectifier default)
D3	1N4007	nearest		question names no diode; using 1N4007 (general-purpose rectifier default)
D4	1N4007	nearest		question names no diode; using 1N4007 (general-purpose rectifier default)
DZ	DZ6V2	synthesized	.model DZ6V2 D(BV=6.2 IBV=5m)	using a synthesised model: Vz=6.2 V anchored at a 5m test current, because the question specifies exactly 6.2 V and a nearby real part would answer a slightly different question

Values that are choices, not givens

These were not stated by the question. They are this tool's engineering judgement, and they are published separately so they are never mistaken for the question's own numbers.

ref	value	origin	rationale
RS	220	designed	drops ~9 V from the ~15.2 V filter output, setting roughly 40 mA total: ~6 mA into the 1k load leaves the zener biased well above its 5 mA knee across the ripple swing [generated, reviewed at input gate]

Design notes

topology: full bridge + C-L-C pi filter + shunt zener with series resistor
the standard topology for this spec; the question names the blocks but not their interconnection or the zener's series resistor [generated, reviewed at input gate]