Generated 2026-08-25 · evaluated by ltspice · manifest version 1
Calculate the output voltage in both load and line regulation and Zener diode current in the regulator circuit shown below using LTspice.
What it asks for:
| measurement | value | run | how | standing |
|---|---|---|---|---|
| vout_nominal | 7.48403263092041 | nominal | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement |
| vb_nominal | 8.292138713092461 | nominal | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement |
| iz_nominal | -0.0036895410157740116 | nominal | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement |
| vout_low | 7.46865177154541 | linesweep | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement at V1 = 12 |
| vout_high | 7.498468399047852 | linesweep | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement at V1 = 20 |
| line_reg_pct | 0.39922369410820396 | derived / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement 100 * (vout_high - vout_low) / vout_low 12 V to 20 V input, normalised to the 12 V output | |
| vout_noload | 7.585122108459473 | loadsweep | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement at RL = 100k |
| vout_fullload | 7.447519779205322 | loadsweep | simulation / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement at RL = 500 |
| load_reg_pct | 1.8476262344191192 | derived / ltspice | EXTERNAL an outside tool computed this, so a bug of ours shows up as disagreement 100 * (vout_noload - vout_fullload) / vout_fullload no-load to full-load, normalised to full-load |
| assertion | run | verdict | what it examined |
|---|---|---|---|
| zener_in_breakdown | nominal / D1 | held | I(D1) against a 0.0001 A minimum reverse current, and its terminal voltage against Vz=8.3 V, at 1 operating point of run 'nominal' |
| bjt_active | nominal / Q1 | held | Vce of Q1 against 0.2 V, and Ib for cut-off, at 1 operating point of run 'nominal' |
| zener_in_breakdown | linesweep / D1 | held | I(D1) against a 0.0001 A minimum reverse current, and its terminal voltage against Vz=8.3 V, at 9 sweep points of run 'linesweep' |
| bjt_active | linesweep / Q1 | held | Vce of Q1 against 0.2 V, and Ib for cut-off, at 9 sweep points of run 'linesweep' |
| zener_in_breakdown | loadsweep / D1 | held | I(D1) against a 0.0001 A minimum reverse current, and its terminal voltage against Vz=8.3 V, at 5 sweep points of run 'loadsweep' |
| bjt_active | loadsweep / Q1 | held | Vce of Q1 against 0.2 V, and Ib for cut-off, at 5 sweep points of run 'loadsweep' |
Every check this target defines ran: no checks were skipped. Stated positively rather than left blank, because an empty section reads the same as an unexamined one.
The layout in these files is generated mechanically — a grid for LTspice, columns by logic depth for Logisim. It is correct, not pretty, and it will not resemble a hand-drawn schematic.
| ref | part | policy | model card | why |
|---|---|---|---|---|
| D1 | DZ8V3 | synthesized | .model DZ8V3 D(BV=8.3 IBV=5m) | using a synthesised model: Vz=8.3 V anchored at a 5m test current, because the question specifies exactly 8.3 V and a nearby real part would answer a slightly different question |
| Q1 | QNPN_BF100 | synthesized | .model QNPN_BF100 NPN(BF=100) | using a synthesised NPN(BF=100) model, the parameters the question specifies |
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